The present invention relates to the field of power distribution systems, and in particular to a power distribution switch fault state current limiter.
In direct-current (DC) power distribution systems a switch is typically used to apply or remove power to a load. The switch typically has a line side, which receives power from a power supply and a load side which is coupled to a load. Current flows through the switch from the line side to the load side.
In power distribution systems with many controllable loads, additional circuitry is added in order to prevent a fault condition occurring in one load from affecting the other switches and loads. An example of a fault condition would be a load side of a switch being shorted to ground, thus shorting out the common power source feeding many other switches and loads. It is common practice to enhance the on/off capability of the switch such that it behaves as a low impedance switch when the load current is within an expected range and behaves as a current limiting switch to afford some protection if a load fault occurs.
FIG. 1A illustrates a high level schematic diagram of a fold back current limit apparatus 10, which provides current limiting during a fault state of a load 20. Fold back current limit apparatus 10 comprises: an electronically controlled switch Q1, implemented in one embodiment, and illustrated herein, as a p-channel metal-oxide-semiconductor field-effect-transistor (PFET); an electronically controlled switch Q2, implemented in one embodiment, and illustrated herein, as a PFET; an electronically controlled switch Q3, implemented in one embodiment, and illustrated herein, as a PFET; a differential amplifier A1, implemented in one embodiment as an operational amplifier (op-amp); a sense resistor RS; a differential amplifier A2, implemented in one embodiment as an op-amp; and a plurality of resistors R1, R2 and R3. In one embodiment, PFET Q2 comprises a single transistor and PFET Q1 comprises 10,000 parallel connected transistors exhibiting identical properties with the transistor of PFET Q2.
The source of each of PFETs Q1 and Q2 are commonly coupled to a line voltage, denoted VLINE, and the gate of PFET Q1 is coupled to the gate of PFET Q2 and to the output of differential amplifier A2. The drain of PFET Q1 is coupled to load 20, to the non-inverting input of differential amplifier A1 and to a first end of resistor R1, the voltage at the junction denoted VLOAD. The inverting input of differential amplifier A1 is coupled to the drain of PFET Q2 and to the source of PFET Q3. The output of differential amplifier A1 is coupled to the gate of PFET Q3. The drain of PFET Q3 is coupled to the non-inverting input of differential amplifier A2 and to a first end of sense resistor RS. The inverting input of differential amplifier A2 is coupled to a second end of resistor R1, to a first end of resistor R2 and to a first end of resistor R3, the voltage at the junction denoted VLOAD. A second end of resistor R2 is coupled to a reference voltage VREF and a second end of resistor R3 is coupled to a common potential. A second end of sense resistor RS is coupled to the common potential.
In operation, PFET Q1 is initially closed and presents a low impedance current path from line voltage VLINE to load 20, the current flowing therethrough denoted ISWITCH. Responsive to the operation of differential amplifier A1 and PFET Q3, the drain voltages of PFETs Q1 and Q2 are equal. As described above, the gates of PFETs Q1 and Q2 are coupled together, as are the sources thereof. As a result, the magnitude of the current flowing through PFET Q2, denoted ICOPY, equals the magnitude of current ISWITCH divided by the dimension ratio of PFETs Q1 and Q2. Particularly, in the embodiment described above, the magnitude of current ICOPY equals ISWITCH/10,000.
As long as no fault is present at load 20, the voltage representation of ICOPY across sense resistor RSENSE will be significantly lower than voltage VLIMIT and differential amplifier A2 will maintain PFETs Q1 and Q2 in a low impedance state. Responsive to a fault at load 20, such as a short circuit, the magnitude of current ISWITCH will increase. When the voltage representation of ICOPY approaches voltage VLIMIT, the output of differential amplifier will become less negative thereby the resistance of PFET Q1 will increase and current ISWITCH will be limited by the value of voltage VLIMIT. Particularly, voltage VLIMIT is arranged such that the maximum magnitude of ISWITCH, denoted ILIMIT, is given as:
                    ILIMIT        =                              10000                          R              RS                                *                      [                                          (                                                                            R                                              R                        ⁢                                                                                                  ⁢                        2                        ⁢                                                                                                        R                            ⁢                                                                                                                  ⁢                            3                                                                                                                                                              R                                                  R                          ⁢                                                                                                          ⁢                          1                                                                    +                                              R                                                  R                          ⁢                                                                                                          ⁢                          2                          ⁢                                                                                                                R                              ⁢                                                                                                                          ⁢                              3                                                                                                                                                            *                  VLOAD                                )                            +                              (                                                                            R                                              R                        ⁢                                                                                                  ⁢                        1                        ⁢                                                                                                        R                            ⁢                                                                                                                  ⁢                            3                                                                                                                                                              R                                                  R                          ⁢                                                                                                          ⁢                          2                                                                    +                                              R                                                  R                          ⁢                                                                                                          ⁢                          1                          ⁢                                                                                                                R                              ⁢                                                                                                                          ⁢                              3                                                                                                                                                            *                  VREF                                )                                      ]                                              EQ        .                                  ⁢        1            where RRS is the resistance of sense resistor RS, RR1 is the resistance of resistor R1, RR2 is the resistance of resistor R2 and RR3 is the resistance of resistor R3. As seen in EQ. 1, when a fault condition occurs across load 20, VLOAD will decrease thereby reducing the value of ILIMIT, in addition to the increase of the magnitude of ISWITCH. As a result, the magnitude of current ISWITCH will be rapidly reduced by PFET Q1.
FIG. 1B illustrates a graph of the power dissipation across PFET Q1, where the x-axis represents resistance values for load 20 in Ohms and the y-axis represents power dissipation values in Watts. Line 30 illustrates the power dissipation across PFET Q1 if the inverting input of differential amplifier A2 were to be coupled to a fixed reference voltage (not shown) and line 40 illustrates the power dissipation across PFET Q1 in fold back current limit apparatus 10. As illustrated, for a low resistance of load 20 the power dissipation of fold back current limit apparatus 10 is lower than the power dissipation with a fixed reference voltage. Unfortunately, for higher load resistances the power dissipation of fold back current limit apparatus 10 becomes greater than the power dissipation with a fixed reference voltage, making fold back current limit apparatus 10 efficient only for low load resistances.
What is desired, and not provided by the prior art, is a fold back current limiter which provides reduced power dissipation across a wide range of load resistances.